CDR circuits (or systems) are generally used to sample an incoming data signal, extract the clock from the incoming data signal, and retime the sampled data. A phase-locked loop (PLL)-based CDR circuit is a conventional type of CDR circuit. By way of example, in a conventional PLL based CDR, a phase detector compares the phase between input data bits from a serial input data stream and a clock signal from a voltage-controlled oscillator (VCO). In response to the phase difference between the input data and the clock, the phase detector generates signals UP and DN. A charge pump drives a current to or from a loop filter according to the UP and DN signals. The loop filter generates a control voltage VCTRL for the VCO based on the UP and DN signals. The loop acts as a feedback control system that tracks the phase of input data stream with the phase of the clock that the loop generates. The dynamics of the loop are generally determined by the open loop gain and the location of open loop zeroes and poles (predominantly in the loop filter).
A problem in systems employing conventional CDR architectures utilizing two CDRs for use in demodulated differential quadrature phase shift keying (DQPSK) modulated data streams is that they are suitable only for full-rate CDRs without data demultiplexing, when the frequencies of the clocks within each CDR are the same as the data rate of the input data bit streams. Otherwise, there exists an uncertainty of relative clock and data phases from the two CDRs and the circuit may operate erroneously. However, many practical CDRs in high speed optical communications use either half-rate or quarter-rate architectures; that is, each CDR may use a clock whose frequency is half (half-rate), a quarter (quarter-rate), or a smaller fraction of the rate of input data stream, in order to cope with high input data rates.